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Lattice Semiconductor
Table 1. User Con?gurable Parameters
CSIX Level 1 IP Core User’s Guide
Number
Parameter
Description
Choice
Default
1
NUM_OF_CHANNELS Number of IP 32-bit channel instantiations.
1,2,3,4
1
2
FIFO_SIZE
FIFO storage capacity. Note that maximum FIFO size 1,024 or 2,048 bytes
1,024 bytes
is dependent on the number of channel instantia-
tions.
For number of channels = 1, FIFO max. size = 2,048
For number of channels > 1, FIFO max. size = 1,024
3
4
AGGREGATION
AGG_SPAN_0
Speci?es whether aggregation is active.
Speci?es number of channels combined to form the
yes, no
0,2,3,4
no
0
?rst aggregate group.
5
AGG_SPAN_1
Speci?es number of channels combined to form the
0,2
0
second aggregate group.
6
BUFFER_TYPE
Buffer type for CSIX interface primary I/O.
LVCMOS, HSTL
LVCMOS
Signal Descriptions
Table 2 de?nes all I/O interface ports available in this core.
Table 2. Signal De?nitions of CSIX Level 1 Core
Signal Name 1
Direction
Width (Bits)
Description
CSIX Interface (These signals are FPGA primary I/Os)
c6_data_in_N_ext[31:0]
c6_parity_in_N_ext
c6_sof_in_N_ext
c6_clk_in_N_ext
c6_data_out_N_ext[31:0]
c6_parity_out_N_ext
c6_sof_out_N_ext
c6_clk_out_N_ext
Input
Input
Input
Input
Output
Output
Output
Output
32
1
1
1
32
1
1
1
Inbound Data
Inbound Parity (Odd)
Inbound Start of Frame
Inbound Clock (100MHz)
Outbound Data
Outbound Parity (odd)
Outbound Start of Frame
Outbound Clock (100MHz)
Generic FIFO Bridge Interface (These signals are buried inside the FPGA)
ib_sine_clk_a_N
ib_sine_data_a_N[35:0]
ib_sine_read_a_N
ib_sine_empty_a_N
ib_sine_data_avail_a_N_n
ib_sine_clk_b_N
ib_sine_data_b_N[35:0]
ib_sine_read_b_N
ib_sine_empty_b_N
ib_sine_data_avail_b_N_n
ob_sine_clk_a_N
ob_sine_data_a_N[35:0]
ob_sine_write_a_N
ob_sine_full_a_N
ob_sine_clk_b_N
ob_sine_data_b_N[35:0]
ob_sine_write_b_N
ob_sine_full_b_N
Input
Output
Input
Output
Output
Input
Output
Input
Output
Output
Input
Input
Input
Output
Input
Input
Input
Output
1
36
1
1
1
1
36
1
1
1
1
36
1
1
1
36
1
1
Inbound Clock, BUS A (100MHz)
Inbound Data, BUS A
Inbound Active High Read Enable, Bus A
Inbound Active High Empty Flag, Bus A
Inbound Active Low Data Available, Bus A
Inbound Clock, Bus B (100MHz)
Inbound Data, Bus B
Inbound Active High Read Enable, Bus B
Inbound Active High Empty Flag, Bus B
Inbound Active Low Data Available, Bus B
Outbound Clock, Bus A (100MHz)
Outbound Data, Bus A
Outbound Active High Write Enable, Bus A
Outbound Active High Full Flag, Bus A
Outbound Clock, Bus B (100MHz)
Outbound Data, Bus B
Outbound Active High Write Enable, Bus B
Outbound Active High Full Flag, Bus B
4
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